Enabling Technologies for 3D IC Integration and Wafer Level Packaging

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration, which is a very complicate subject. It involves component and system designs, FAB, packaging, and testing; and materials and equipment suppliers. The key enabling technologies for 3D IC integration and wafer-level Packaging (WLP) are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. Most of the materials are based on the technical papers published within the past 3 years by the instructor and others.

This and all other courses are available for On Site Training


HOW YOU WILL BENEFIT:
  • Understand all important aspects of 3D IC integration and WLP
  • Understand the impact of TSV on 3D IC Integration and WLP
  • Know the 5 key process steps of TSV
  • Understand the impacts of TSV interposers on thermal and mechanical performance
  • Know how to fabricate and characterize lead-free solder microbumps
  • Know how to assemble lead-free solder microbumps and their reliability
  • Know how to measure the strength of thin chips
  • Know how to do wafer thinning and thin-wafer handling
  • Know how to do low-temperature bonding for C2W and W2W stacking
  • Know how to do thermal management of 3D IC stacking
  • Integrating 3D IC integration and WLP into your SMT assembly

COURSE COVERS:
  • Overview of 3D IC integration and packaging
  • KGD issues and solutions
  • TSV forming (DRIE and laser)
  • TSV dielectric, barrier, and seed-metal layers
  • TSV filling and CMP
  • Effects of TSV interposer on thermal performances
  • Effects of TSV interposer on mechanical performances
  • Stress sensor for thin-chip strength measurement
  • Wafer thinning and thin-wafer handling
  • Low-cost microbumps (?25µm pitch): fabrication and characterization
  • Low-cost microbumps (?25µm pitch): assembly and reliability
  • Low temperature (<200oC) C2W bonding
  • Low temperature (<200oC) W2W bonding
  • Thermal management (design charts and guidelines) for 3D stacked chips
  • Integrated liquid cooling solutions for 3D stacked modules
  • Hot spots in thin chips for 3D stacking
  • Supply chain for 3D IC integration and packaging
  • Critical issues in adopting TSV and 3D IC integration

WHO SHOULD ATTEND?
  • Engineers and Managers involved with any aspect of the electronics industry
  • R & D personnel
  • Scientists


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