Bypassing (Including BGA's) Crosstalk and Differential Signaling

In today’s high-frequency designs, clock speeds of 1 GHz and edge rates less than 1 nsec are common. These high frequencies and their harmonics must be bypassed properly between power and ground to insure power delivery, switching fidelity and control of radiated emissions. To ensure that the power delivery system meets its objectives, the intelligent placement, value, size and type of capacitors must be achieved. Also, at higher frequencies the die and interplane capacitance must be optimized. Proper via placement for return current pathway minimization, laying out digital/analog interfaces, ours (Cu fills) and splits must be carefully analyzed. This all-day session will illustrate a layout process that achieves 0.1 ohm up to the knee frequency and provides methods to minimize serial/parallel resonance and achieve constant ESR.