Introduction to CMOS Layout

The Introduction to CMOS Layout seminar is designed to guide the attendee to an entry level understanding of the actual processes used in generating a topological layout for a CMOS integrated circuit. The seminar will also walk the attendee through the major steps involved in determining what is to be built as defined by marketing, circuit implementation by design engineering, and actual floor planning and transistor layout techniques. This is followed by descriptions of the processes that follow the layout through to the finished product including the effect of die size on yield.

After completing the two day Introduction to CMOS Layout seminar, the attendee will be able relate and understand the major elements of an IC development flow. This includes being able to draw circuits of simple complexity using CMOS transistors and good industry layout practices and to determine whether it is correct to the schematic requirements. This instructional program is especially well suited to any individual or company that works with the semiconductor industry or any field that is related to this industry. This includes education where an electronic curriculum or support subject is taught. It is a must for new college graduates who will be entering the dynamic semiconductor industry along with Computer Science Engineers who write software used for layout and layout verification, and Reliability and Test Engineering organizations.

This and all other courses are available as On Site Training


WHAT THE COURSE COVERS:

  • Transistor Cross Section
  • Building CMOS Transistors
  • Logic to Schematic
  • Truth Tables
  • Schematic to Layout / Layout - How to
  • Block & Cell Planning
  • Power Distribution
  • Standard Cells
  • Vias and Contacts
  • Busses and Bus Routing
  • Gate Layout Practices
  • Legging Devices
  • Transistor Device Matching
  • Poly as Interconnect
  • Substrate and Well Taps
  • Latchup
  • Self Heating and Electromigration
  • Resistors, Capacitors
  • Diodes and ESD Devices
  • Guardrings
  • Dieseal
  • Bonding Pads
  • Laser Targets
  • Fuses
  • Hierarchy
  • Yield
  • Layout Quality Checklist

WHO SHOULD ATTEND?

  • Layout Designers
  • Software Tool Designers
  • Mask Makers
  • CAD Engineers
  • Tool Developers
  • Circuit Designers
  • Reliability Engineers
  • Test Engineers

This course includes our CMOS Layout manual with color illustrations for each student.

"We Exceed Your Expectations!"

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