Introduction to CMOS Logic Design

The course is designed for the personnel supporting the design of integrated circuits. The main objectives are to cover logic design, design concepts, design flow, physical layout and EDA tools. This course is instructed at the lay person level.

Currently Scheduled Open Course Dates:

October 8, 2008 ~ Dallas, TX

Register now for the next session!

This and all other courses are availalbe as On Site Training

WHAT THIS COURSE COVERS:
  • Explain Basic Electronics Concepts
  • Fundamentals of ICs: Explain basic technologies used to design and fabricate ICs.
  • Logic Design Concepts
  • Understanding Digital Logic
  • Gate Function, Delay, Area
  • Combinging Gates into Standard Cells
  • Concept of a Standard Cell Library
  • Logic Design with Pencil and Paper
  • Logic Design with Synthesis Tools
  • Simulation to Check Functionality
  • Timing Analysis to Check Speed
  • Designing Logic for Testability
  • Formal Equivalence Checking
  • Physical Layout Concepts
  • Concept of Chip Floorplan
  • Logical Netlist to Placed Gates
  • Global and Detail Routing
  • Tapeout and Mask Generation
  • Comparison of IC Design Methodologies
  • Emerging Design Layout Trends
  • Domain Specific Design
  • Managing Chip Complexity
  • Design Team Roles
  • Adapting to Deep Submicron
  • Wafer Fabrication
  • Assembly, Packaging and Test

WHO SHOULD ATTEND?
  • Junior Design Engineers
  • CAD Engineers
  • Human Resources
  • Financial Planners
  • Sales/Marketing
  • Public Relations
  • Technical Writers
  • R & M Tech's
  • EDA Tool Vendors
  • Design Support Personnel
  • Operators
  • Legal Counsel
  • Production
  • Training
  • Buyers
  • Layout Designers
  • EDA Engineers
  • Customer Service
  • Administration
  • Production Planners
  • Quality
  • Engineering
  • Tool and Material Vendors
  • IT Engineers
This course includes an ASIC Design manual with color illustrations and course handouts.

INSTRUCTOR:

Chip Dancek spent ten years at Synopsys where he developed several of the company's most successful customer-training workshops. Prior to joining Synopsys, he worked at Cadence, Teradyne, Silicon Compilers, and Intel. He has presented workshops and seminars across North America, Europe, and Asia. Chip teaches basic and advanced logic design using Verilog or VHDL at the University of California. He holds an MSEE from the University of Wisconsin, and an MS in Solid-State Physics from New York Polytechnic University.


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