Intro – Test Problems
- Expensive / Time Consuming / Complicated / Frequency
- Problems – Design, Fabrication, Assembly, and Reliability
- Pin Count / Accuracy
Semiconductor Trends
- Moore’s Law / Frequency / Die Size / Cost / Functions
- Transistor “Scaling” – trends and effects
Fault Models
- Introduction – Behavioral Level / Gate Level (RTL)
- Component Level / DC and AC Fault Models
Automatic Test Pattern Generation
- What is ATPG? / Structural Test
- Overview of the ATPG Process
- Targets - Cone of Logic / Injecting Faults
- Generator Vectors
- Reconvergent Inputs / Reconvergent Fanouts
- ATPG vector validation
- Fault Coverage / Fault Grading
Design for test (DFT) Introduction
- Functional vs. Structural Test / Ad-Hoc vs. Structured DFT
- DFT methods / Full Scan vs. Partial Scan / DFT benefits
DC Scan
- Implementing Logic Scan / Flops – Mux-D / ATPG and Scan Logic
- Single, Multiple Chains / Scan Terminology / Shifting Scan Data
- Scan Timing Diagrams / Shared Scan interface functions
- Testing Scan Logic / Data Alignment Issues / DC Scan Tests Fail
AC Scan
- Why perform AC Scan? / Delay Fault Models and AC Scan
- Delay Path Distribution / Dynamic Hazards
- Robust Delay Rules, Tests / AC Scan Terminology
- Strategies for Delay Tests
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How AC Scan Works
- Launch On Shift (L-O-S) / Functional Launch / AC Scan Debug
- Using AC Scan / Clocks and Phase Lock Loops / Chop Clocks
Boundary Scan 1149.1 IEEE Standard - JTAG
- Introduction to Boundary Scan and JTAG
- Why it is needed (PCB test requirements)
- The IEEE 1149.1 Standard – what’s defined
- Boundary Scan Register functions
- TAP Controllers and dedicated pins
- TAP 16 State Machine
- TAP Operations
- Boundary Scan Instructions
- Instruction Behavior / Bypass Register
- Boundary Scan Register hardware
- Identification Register
- BS Timing
- Using BS for parametric tests
- Troubleshooting with Boundary Scan
- Testing Boundary Scan hardware
Built-In Self Test (BIST) –
- BIST defined / BIST applications / Logic BIST Architecture
- Memory BIST Architecture, Algorithms / BIST Clocking
- Pseudo-Random-Pattern-Generation (PRPG)
- Linear Feedback Shift Register (LFSR) / LFSR Designs
- Seed Codes, Polynomials / Correlated Data Issues
- Phase Shifters, Spreaders, Broadcasters
- Output Compression – Multiple Input Shift Registers (MISR)
- Output Signature / Logic BIST Test Sequence
IO BIST – Reduced Pin Count Testing (RPCT)
- Why IO BIST / IO BIST pin circuitry / No Contact Shorts Test
- Reduced Pin Count Testing, Basic IO Functional Test
- IIL/IIH No Contact Leakage Tests
DFT and ATE Systems
- ATE System overview – types of test systems
- Uses for each type of system / Introduction to DFT ATE
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