Understanding Error Analysis and Jitter

It's 10 o'clock, do you know where your BER is?
Is your pattern in synch?
Do you know your RJ from DJ? How about DDJ, PJ, SJ, ISI, DCD,...?
How open is your eye?
Are you in phase with your noise?

At high data rates, digital errors are a huge problem. With emerging Gbps+ standards requiring a Bit Error Ratio (BER) better than one in a trillion, technicians and engineers must recognize when a component or system has an error-causing defect. The culprit is usually jitter. This course delivers a complete conceptual understanding of bit error ratio and jitter analysis with a thorough description of jitter causes and how to diagnose them, including a conceptual introduction to the new high data rate specifications. This course will be tailored to address your team’s specific needs: FibreChannel, USB, PCI Express, SAS, SATA, FBDIMM, SONET/SDH, RapidIO, DisplayPort or ten gigabit Ethernet.


This Course Will Enable Participants to:
  • Explain the difference between ideal and real digital signals and problems that occur as data rates increase
  • Measure and understand the meaning of BER, “bathtub plots” and Q-factor
  • Determine the source of digital errors
  • Recognize the difference between voltage noise and jitter
  • Analyze clock signals in both the time and frequency domains
  • Explain concepts of jitter generation, transfer and tolerance
  • Recognize the advantages and challenges of embedded clocks and clock recovery
  • Diagnose jitter and noise problems on an oscilloscope and/or a bit error ratio tester
  • Identify the sources of RJ, DJ, PJ, SJ, ISI, DDJ, DCD, BUJ
  • Estimate the bit error ratio of a system, given the jitter of its components
  • Understand the emerging high data rate PHY specifications

This and and all other courses are available for On Site Training

WHAT THE COURSE COVERS:
    Part 1 - Overview
  • Digital systems
  • Ideal digital signals
  • Real digital waveforms
  • Eye Diagrams
  • Digital errors
  • The Bit Error Ratio (BER)
  • Testing BER, Pt 1: the BERT
  • Intro to Clocks and Timing
  • Voltage Noise and Phase Noise
  • Jitter
  • Noise
  • Clock Jitter – legacy techniques

    • SONET-style Jitter
  • Jitter analysis in the new serial data technologies


    • Part 2 – BER analysis
  • Test Patterns for different purposes
  • Q-factor
  • Clocks and timing
  • Testing BER, Pt 2: The Bathtub Plot
  • “Total Jitter” and eye-closure
  • The BER-Contour


    Part 3 – Jitter
  • Jitter from voltage noise
  • Jitter from phase noise
  • Peak-to-peak jitter
  • Random and Deterministic Jitter – RJ and DJ
  • RJ, PJ, SJ, ISI, DCD, DDJ
  • Causes of jitter
  • Clock Recovery and jitter bandwidth
  • Spread Spectrum Clocking


    • Part 4 – Diagnosing Problems with Jitter
  • Errors caused by jitter in different systems
  • Clock recovery and jitter
  • Diagnosing Jitter on an oscilloscope
  • Jitter analysis on a BERT
  • Combining jitter sources to estimate a system BER
  • Introduction to FibreChannel, USB, RapidIO, DisplayPort, GbE, FBDIMM, SAS, SATA, PCI Express – generations 1-3
  • Diagnostic vs compliance testing
  • The new jitter tolerance tests – stressed eyes

WHO SHOULD ATTEND?
  • Technicians
  • Engineers
  • Scientists
  • Engineering and physics students

"We Exceed Your Expectations!"

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