Low-Cost Flip Chip, WLCSP & Lead Free Technologies
The major trend in electronics industry today is to make products more personal by making them smarter,
lighter, smaller, thinner, shorter, and faster, while at the same time making them more friendly, functional,
powerful, reliable, and less expensive. The last few years witnessed an explosive growth in the research and
development efforts devoted to solder bumped flip chip, direct chip attach (DCA), wafer level chip scale
package (WLCSP), plastic ball grid array (PBGA), and Microvia as a direct result of the rapid growth of
surface mount technology and miniaturization. Many major equipment makers and leading electronic companies
are now gearing up for these emerging and advanced packaging technologies. To remain in the forefront of this
fast-moving industry, requires in-depth knowledge and understanding and technical know-how of the implementation
of these technologies into the products and assembly lines.
This one-day course will discuss vital issues such as the economic, design, material, process, equipment,
quality, and reliability relating specifically to this growing industry and address key aspects and questions
on microvia buildup high density interconnects, WLCSP, DCA, FC-PBGA, and lead free solder bumped flip chip
packaging and assembly techniques. After completing this tutorial, you will be able to choose a
cost-effective packaging design and high-yield manufacturing process.
WHAT THE COURSE COVERS: |
- IC Packaging Trends
- Chip Level Interconnects
- Lead Free Solders
- High Density, Microvia, PCB and Substrates
- Flip Chip on Board (FCOB) with Solderless Materials
- Flip Chip on Board with Conventional Underfills
- Flip Chip on Board with Imperfect Underfills
- Flip Chip on Board with No-Flow Underfills
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- Flip Chip on Board with Imperfect Underfills
- Thermal Management of Flip Chip on Board
- Wafer Level Packaging
- Solder Bumped Flip Chip on Micro VIP Substrates
- Solderless Flip Chip with Adhesive
- Solder Bumped Flip Chip in PBGA Packages
- Summary and Discussions
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WHO SHOULD ATTEND? |
- Component Engineer
- Packaging Engineer
- Design Engineer
- Material Engineer
- Process Engineer
- Equipment Engineer
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- Reliability Engineer
- Quality Control Engineer
- Manufacturing Engineer
- Marketing Engineer
- Sales Engineer
or Any Managers of the above
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INSTRUCTOR: |
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John Lau, Ph.D., P.E., is an Interconnection Technology Scientist
at Agilent Technologies, Inc. in Santa Clara, CA. Previously he was President of Express Packaging Systems and a
Senior Individual Contributor at Hewlett-Packard Laboratories. Dr. Lau is a widely recognized expert at cost
effective IC packaging technolgies, DFM, electronic component and system reliability, and the management of
low-cost, high volume manufacturing. The recipient of many honors, Dr. Lau is a Fellow of ASME and a Fellow
of IEEE. He has been Associate Editor for IEEE Transactions on CPMT and Associate Editor for ASME Transactions
and the Journal of Electronic Packaging, as well as Program Chair for several major packaging events. He has written
14 books on packaging, has authored more than 150 technical papers in this area, and has conducted over 200 technical
lectures and workshops related to packaging.
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"We Exceed Your Expectations!"
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