- Lumped vs. distributed systems
- Four kinds of reactance
- Ordinary and mutual capacitance and inductance
- EM fields
- Geometry, C, L, Z0, interrelationships C and L resonance
- High- Speed Properties of Logic Gates
- Quiescent vs. active dissipation
- Driving capacitive loads
- Input power and external power
- TTL, CMOS, SiGe, In Pn, ECL, and GaAs; Output power, speed and engineering disciplines, Dv, di effects and voltage margins
- ICs: Cu vs. Al, what are the issues?
- Low –k dielectrics
- Intersymbol interference (ISI), eye diagrams and jitter
- Shoot through current (SSO) and how to minimize it
- Ground bounce, lead inductance, simultaneous switching noise (SSN)
- Electronic packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP and their relationship to SI
- Lead capacitance and thermal considerations
- Measurement Techniques
- Rise time and bandwidth of oscilloscopes and probes
- Self-inductance and spurious signal pickup of a probe ground loop
- How probes load down a circuit special probing fixtures
- Avoiding pickup from probe shield currents
- Communications-SONET, SERDES, OC 192/768, fiber
- Slowing down the system clock
- Observing metastable states in flip-flops
- Transmission Lines
- The quality factor, Q, and why lumped circuits can ring and cause EMI
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- Infinite uniform transmission line
- Effects of source and load impedance
- Determining line impedance and propagation delay using TDR and VNA
- The capacitive load –Z0 and propagation delay
- Matching Z0 with alturations- minimizing the C load
- Characteristics of T lines
- Terminations
- End/Source/Middle terminators
- AC biasing for end terminators
- Hairball networks, bifurcated lines and capacitive stubs
- Terminating differentials-eliminating common mode and minimizing power
- Diode and active terminators, resistor selection and crosstalk in terminators
- VIAS
- Mechanical properties of vias
- Capacitance and inductance of vias
- Through hole, blind, buried, micro vias
- Intelligent vias and auto routers
- Via discontinuity and via resonance
- Clock Distribution
- Timing margin and clock skew
- Using low-impedance drivers and clock distribution
- Source termination of multiple clock lines
- Delay adjustments-serpentine traces/DACs and varisters for dynamic delay
- Controlling clock signal duty cycle using the integrator
- Source synchronous clocking, DDR and RDRAN
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