IC Development Cycle

This live seminar equips marketing professionals, program managers, executives and other key decision-makers with an industry-insider’s grasp of the IC development cycle, from product concept to box stock. By combining live instruction and team exercises with 3-D, animated graphics, this two-day seminar breaks through the jargon barrier, presenting technical concepts in plain, everyday language. This course relates the nuts and bolts of semiconductor technology to the real-world business, pricing and selling units, and makes realistic commitments to OEM/ODMs.

Beginning with the basics, it describes each phase in IC Development flow. It begins with defining the architectural features their competitive edge, to how engineers design in benchmark-busting performance, to fabricating the design in silicon. It explores key trade-offs, clarifies the critical roles of System Engineering and Program Management, and clearly explains terms like superscalar pipeline, NUMA, cache, cache hit, tape-out, reticle fix and rocket lot.

We offer this and all courses as On Site Training


WHAT THE COURSE COVERS:
  • How a typical IC product goes through product definition, design, debug, and production
  • How the same basic IC design is configured, fused, binned, and retargeted into a cascade of products
  • Why higher speed means more power and lower yield also how CD retargeting enhances revenue
  • What exactly is a desktop equivalent and how it helps determine pricing for a mobile product
  • What impact a major and minor mask revisions can have on cycle time


WHO SHOULD ATTEND?
  • Professionals who need to make critical decisions, interpret data, build roadmaps, and engage with customers based on a firm grasp of the driving factors behind semiconductor economics. This includes shrinking feature size, yield roll-off, power/performance trade-offs, product bining, wafer-fab metrics like DPW, SPW and DTS.
  • Those who find their corporate role increasingly expanding beyond the traditional limits of their core competency.

This is a 2 day course and each student will get a comprehensive set of course notes.


INSTRUCTOR:

Chip Dancak Chip spent ten years at Synopsys where he developed several of the company's most successful customer-training workshops. Prior to joining Synopsys, he worked at Cadence, Teradyne, Silicon Compilers, and Intel. He has presented workshops and seminars across North America, Europe, and Asia.

He holds an MSEE from the University of Wisconsin, and an MS in Solid-State Physics from New York Polytechnic University.


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