Intro to Integrated Yield Management

"Fabless Version"

The focus is on fast PRODUCT "TIME-TO-MONEY" for FABLESS COMPANIES. Advanced semiconductor product & process characterization, control, cycle time, and yield methods, applicable across the design, foundry, yield and test spectrums, are featured. This cross-functional fabless / foundry approach integrates roles and responsibilities, which are vital for fast new product introduction, maximum fab output and shortest time-to-money. Topics include product life cycles; new product introduction; managing defects; test structures and how they speed the yield ramp; root cause analysis; synchronized manufacturing; foundry process control & future technology directions; and project management, including problem solving. Before committing a design to silicon, we will predict entitled yield, identify yield limiting design features and describe design/foundry tradeoffs. To maximize output, we will characterize the process for yield limiting factors, look at design layout options, and interpret the results of test structures, micro models, recipe control, pattern defect control. We will show how to implement & manage many actions/metrics/controls into project management output meetings.

We offer this and all courses as On Site Training


WHAT THE COURSE COVERS:
  • Advanced Semiconductor Product & Process Characterization
  • Control
  • Cycle Time
  • Yield Methods
  • Yield and Test Spectrums
  • Product Life Cycles
  • New Product Introduction
  • Managing Defects
  • Test Structures and how they Speed the Yield Ramp
  • Root Cause Analysis
  • Synchronized Manufacturing
  • Foundry Process Control
  • Future Technology Directions
  • Project Management including problem solving
  • Predict Entitled Yield Before Committing a Design to Silicon
  • Identify Yield Limiting Design Features
  • Describe Design/Foundry Tradeoffs
  • Characterize the Process for Yield Limiting Factors
  • Look at Design Layout Options
  • Interpret the Results of Test Structures, Micro Models, Recipe Control, Pattern Defect Control
  • Learn how to Implement & Manage Many Actions/ metrics/ controls into Project Management Output Meetings
  • Learn to Distinguish between Design/ Foundry/ Test/ Assembly Issues
  • Learn the Difference Between Faults & Defects
  • Learn how Defects are Distributed & Modeled
  • Learn the Effect of Defects on Product Yield
  • Learn the Effect of Die-Size/Device- Design- Density/ Defect-Density on Yield
  • Learn how to Make a Design More Robust
  • Learn about Typical Defect Structures
  • Learn to Seperate Systematic from Random Defects
  • Learn Cluster, Schmoo, Zone, Pattern, Design/ Parametric Sensitivity and Electrical/Physical Analysis Techniques
  • Learn Why Foundry Issues are Important to Fabless Design
  • Learn about in-situ/short/long loops & OPC/PSM/Strained-Silicon/SOI/CMP
  • Learn how to Structure & Manage Product Yield Meetings
  • Learn how to Solve Problems Between Design & Foundry

WHO SHOULD ATTEND?
Engineers, Managers and Support Personnel working on and/or serving in:

  • Device Structure Development
  • Process Development
  • Process Integration
  • Process Operations
  • Product Design
  • Product Engineering
  • Design Library Characterization
  • Yield Characterization
  • Physical Failure Analysis
  • Test and Test Analysis
  • Fab / Foundry Operations Support

INSTRUCTOR:

Bob Carlson was a seasoned IBM Microelectronics’ engineer & manager. In the early 1970’s, he developed many early yield enhancement management techniques & test structures. In the late 70’s, Bob’s photo engineering team maximized 3000 WSD fab output with world-class photo limited yields. When the early 80’s, came along his fab engineering team brought on line the world’s 1st 5-inch CMOS fab & piloted the 1st yielding 8-inch wafers. Int he mid 80’s, Bob was Manager of IBM’s high performance bipolar semiconductor development & pre-production fab where his team developed the fastest, densest bipolar memory & logic products for IBM mainframes, using industry 1st processes: FEOL poly trench & poly emitter; BEOL 4-level-metal / CMP / Tungsten-stud / e-beam-direct-write. Early 90’s, Bob was an IBM Cycle Time Consultant. In 1994 he left IBM to provide industry Cycle Time & Yield consulting. Bob has a BS & MS Degrees in Electrical Engineering from the University of Maine.


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