CMOS Latchup Design and Process Solutions

This 2 day course deals with the issues of CMOS latchup and how to prevent it using design and process solutions. Also discuss are the physics and theory, latchup conditions, latchup test structures, latchup characterization and classes.

Next Available Course Dates:

, 2008 ~ Dallas, TX

Register now for the next session!

We offer this and all courses as On Site Training

WHAT THE COURSE COVERS:

  • Latchup Physics and Theory
  • Latchup Circuit Schematics
  • Overshoot
  • Undershoot
  • Latchup Initation Conditions
  • PNP Initiated Latchup
  • NPN Initiated Latchup
  • Latchup Criterion
  • Beta Product Relationship
  • Generalized Tetrode Relationship
  • SAFE Region
  • Latchup Propagation
  • Latchup Domino Effect
  • LatchUp - Classes of Latchup
  • D.C. and Transient Latchup
  • Internal Latchup and External Latchup
  • Single Event Upset Initiated Latchup
  • Power Supply Latchup
  • Input Pin Latchup
  • Pin-to-Pin
  • Inter-circuit latchup
  • Intra-circuit latchup
  • ESD Power Clamp Initiated Latchup
  • ESD Input Node Initiated Latchup
  • Latchup Test Structures
  • PNPN Test Structure
  • PNPN Test Structures with Guard Rings for Internal Latchup
  • Triple Well PNPN Test Structures
  • Deep Trench PNPN Test Structures for BiCMOS
  • Guard Ring Test Structures
  • Guard Ring Structures for Internal Latchup
  • Guard Ring Structures for External Latchup Characterization
  • Injector-Collector Structures
  • Guard Ring Theory
  • Guard Ring Efficiency Characterization
  • Lateral Beta Evaluation
  • Latchup Characterization
  • D.C Characterization Techniques
  • Well-Substrate Resistance Characterization Techniques
  • Transient latchup Characterization Techniques
  • Automated Test Equipment
  • External Latchup Characterization
  • Injector and Collector
  • Relationship of Injection current and Circuit Robustness
  • Latchup Propagation
  • Latchup Device Simulation
  • P+/N+ Scaling
  • STI Scaling
  • Well Scaling
  • Latchup Process Solutions
  • Heavily Doped Substrates
  • Diffused N-Well
  • Retrograde N-Wells
  • P-Wells
  • P+ Connecting Implants
  • Shallow Trench Isolation
  • Polysilicon Filled Deep Trench
  • Biased Deep Trench
  • Trench Isolation
  • Heavily Doped Buried Layers (HDBL)
  • Buried Grids (BG)
  • Latchup Photoemission Characterization – Optical Techniques
  • Optical Techniques and Emission Microscope (EMMI) Tools
  • Transmission Line Pulse – Pico-second Current Analysis (PICA) Tool and Animation
  • Latchup Circuit Solutions
  • Passive and Active Guard Rings
  • Anti-Overshoot Circuits
  • Voltage and Current Supply Solutions
  • Sequence Independent Power Supply Circuits
  • Latchup Computer Aided Design (CAD) Tools

WHO SHOULD ATTEND?

  • Circuit Designers
  • R & D
  • Product Engineers
  • Test Engineers
  • Process Engineers
  • Anyone Needing an Understanding of Latchup Issues

"We Exceed Your Expectations!"

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