Mastering High Speed Serial-Data Technology

Why is serial better than parallel?
What do you really need to test?
Does compliance assure interoperability?
Do you know what’s closing your eyes?
How deep is your bathtub?
Do you believe in dual-Dirac?
Is your Q-scale on straight?
Can you calculate TJ from RJ, PJ, ISI, DCD, DDJ?

The new High Speed Serial-Data standards are challenging engineers to master new concepts – after this course, you will be an expert. From 2.5 Gb/s and higher, trouble comes in many different forms and we cover every one: From distortion, random jitter and noise at the transmitter, to inter-symbol interference and crosstalk on circuit boards, backplanes and cables, to clock and data recovery at the receiver. Using examples from cutting edge serial technologies, this intense one-day course delivers a complete technical understanding of potential trouble spots in high speed serial components and systems, how the standards attempt to insure interoperability, and the interdependence of problems. This course will be tailored to address your team’s specific needs: USB, PCI Express, SAS, SATA, FBDIMM, RapidIO, DisplayPort, ten gigabit Ethernet and/or etc.

This Course Will Enable Participants to:
  • Master emerging high speed serial-data technologies
  • Identify those compliance tests that are necessary to assure interoperability
  • Describe the relationship between jitter and phase noise and amplitude noise
  • Distinguish crosstalk from BUJ
  • Debug components and systems with oscilloscopes, phase noise analyzers, spectrum analyzers, bit error ratio testers, and know which tool to use for different problems.
  • Master the dual-Dirac model, Q-scale, bathtub plots, and TJ(BER)
  • Calculate TJ(BER) and pulse width shrinkage from jitter components
  • Understand the advantages and disadvantages of embedded and distributed clocks and their effect on system jitter and BER

This and and all other courses are available for On Site Training

WHAT THE COURSE COVERS:
    Part 1 – High Speed Serial-Data Technology
  • High Speed Serial-Data systems
  • Differential signaling
  • Embedded vs distributed clocks
  • Clocks and oscillators
  • Trouble at the transmitter: RJ and DCD
  • Trouble in the transmission path: ISI, DDJ, PJ, Crosstalk and BUJ
  • Trouble at the receiver: Receiver tolerance and BER


    • Part 2 – Sources of trouble
  • The digital myth and analog reality
  • Random Jitter and the central limit theorem
  • Aside: bluffer’s guide to probability and statistics
  • Dispersion, skin effect and inter-symbol interference
  • Electromagnetic interference and periodic jitter
  • How component problems combine into system problems
  • Crosstalk: NEXT, FEXT, and clocks
  • The unique problem of crosstalk and test instrumentation


    • Part 3 – Clocks and Clock Recovery
  • Jitter in the frequency domain
  • PLL-based CDR
  • Phase Interpolator based CDR
  • Spread spectrum clocking
  • The problem of delay


    Part 4 – Total Jitter
  • In search of peak-to-peak jitter
  • TJ(BER): Total Jitter at a Bit Error Ratio
  • The Dual Dirac Model
  • Bathtub plots and Q-Scale
  • Eye opening and pulse width shrinkage
  • Combining component jitter to estimate system jitter
  • Measuring vs estimating TJ(BER)


    • Part 5 – Diagnostic and compliance testing
  • The differences between diagnostic and compliance testing
  • Transmitter testing – oscilloscopes and BERTs
  • Backplane, PCB, cable testing – S-parameters and simulation
  • Analyzing closed eyes
  • Introduction to deemphasis and equalization
  • Introduction to stressed eye receiver tolerance tests
  • Accuracy of different test techniques


    • Part 6 – High Speed Serial-Data Standards
  • Similarities and differences of the standards
  • Examination of the standard(s) you’re working on

WHO SHOULD ATTEND?
  • Design and test engineers, digital and RF engineers, scientists, senior level EE and physics students
"We Exceed Your Expectations!"

Return to Home Page
Return to Course Schedule