Board-Level Guides
- Initialization, signal monitoring, feedback, oscillator control, and ambiguity groups; LSI/VLSI test guides: partitioning and bus
visibility, software/hardware control, controlling microprocessors, three-state buses, memory elements, synchronization, and clock control-examples
of controlling CPU architectures for in-circuit test; mechanical testability guides: accessibility, board layout and board orientation, standard grids,
design for simplicity/assembly/manufacturabilty; Analog and hybrid guides: signal interfacing, analog test points and partitioning analog circuitry;
Scoring testability: three methods for scoring design testability and identifying areas of untestable designs
Routing Board Layout Design Issues
- Board size, parts placement, large components, test pads, vias, standard cells, auto drill/probe, and wire wrap issues; Spacing, skewing error
sources, actual pad size, chip shooters, vision systems, coplanarity; CAD drill tapes, top/bottom side registration issues, tooling holes accuracy
requirements, test probes, daughter boards, clam shell fixtures, test top modules, the lattice probe structure.
Bareboard Test Issues
- Effect of discrete components, SMT, and both buried and distributive capacitance on EMI, stripline and impedance controlled boards, and
curved traces; Testing blind and buried vias; Bareboard test issues for high-density routing: resistance, frequency, and signal quality; Today’s
bareboard test capabilities: megohm level, safety features, speed fixturing enhancements and programming; Automation techniques for transferring
router (data set) files directly to the B/B tester (i.e., eliminating software coding); Flying probe testing and the concept of rapid
prototypes (i.e., testing just-in-time).
Student Participation
- A variety of boards will be displayed to illustrate concerns of testing bareboards. Also, videos will be presented showing methods of
performing clam shell and flying probe bareboard test.
In-Circuit Issues
- Standard cells and the ability to via electrical nodes: No-clean solder paste and ICT bed-of-nails (BON) contamination, vias under components-pros
and cons; Purpose of 100% nodal visibility to the bottom of the board; Design rule checker requirements; Testing ASICs and MCMs; Board stress:
what it is and how to eliminate it; test pad size: fixture tolerances, pin tolerances, and error sources in the B/B; Standard guides for automatic
BONs fixturing; Why test spares; Detection of the fault cause: solder, components, printing, chip shooting, cleaning, and the human element-ICT
must detect the fault, isolate the fault, and define the fault cause; Backdriving: requirements for CPU bus architectures, ASICs, and active
components; What to do when the IC model is not in the library; Why intelligent ICT is the best SPC tool in the factory; What’s new in wireless
fixtures, magnetic plate, capacitive plate and reverse diode testing-how they work and what they can do for your company’s ICT test capability;
Can a board level functional test be completely eliminated; industry examples. Student Participation: A variety of populated PCBs and videos will
be used to reflect the concerns of testing PCBs with today’s high-density requirements.
Board Contamination
- What causes it and what are the effects in electrical degradation, moisture absorption, and corrosive ionics; Surface insulation resistance: how to
test it, defining acceptable limits; Ionograph testing, copper mirror test, solder mask corrosion test, and solderablity test: what they are and when
they should be used
Vision
- Types: Microscope, X-ray, laser, AOI and laminography. What can they test, where should they be used and
how they can affect ppm defects.
Flying Probe (FP)
- Speed, accuracy, capabilities, testing BGA, CSP, TAB, FC, and COB using FP. Emerging Technology packages, videos and X8 magnifiers will be
used to illustrate the need for Vision and Flying Probe.
IEEE 1149.1 Boundary SCAN
- Why boundary SCAN: the ever-increasing electrical node-I/O pin visibility ratio and increasing lack of coverage using bed of nails; Understanding
the spec: TAP control, data instruction registers, the five test instruction, running BIST; SCAN for ICT, board and system functional test-does it work;
ICT testers and test software; The view of Silicon foundries, ASIC designers, IC manufacturers, and test engineer; SCAN vs. bed-of-nails, nodal visibility,
circuit performance, and silicon overhead.
Test Strategy and Rapid Prototypes
- Achieving low ppm factory defects, eliminating the hidden factory, and achieving maximum payback for test dollars; Product vs. strategy:
high/low volume, number of PWA types, and PWA complexity; JIT and ppm defects; Eliminating “no-payback” test; How to minimize time for
bareboard, ICT, and functional test; How to correct the factory; SPC, JIT, and DFS and minimize cost.
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