Verilog Design

Verilog is the most prevalent hardware description language (HDL) used to verify, synthesize, and test digital hardware. It uses C-like statements to describe and stimulate logic. This course focuses on IEEE standard Verilog-2001, enhanced for complex system-on-chip ASICs or platform FPGAs. All topics include systematic examples and individual exercises, reinforcing the use of Verilog-2001 constructs to efficiently describe or verify register-transfer level (RTL) hardware. Several levels of abstraction are covered. Nuances of the language—like nonblocking/blocking assignments and net/variable types—are explained in depth. Key ’01 enhancements—like generate loops— are shown. The instructor will demo usage of synthesis and simulation tools. By the end of the course, each student will be able to code a realistic Verilog module or testbench.

Next Available Course Dates:

October 9-10, 2008 ~ Dallas, TX

Register now for the next session!

This and all other courses are available for On Site Training


WHAT THE COURSE COVERS:
  • Day 1: Verification
  • Intent of Language
  • Evolution of Verilog
  • Levels of Abstraction
  • Three Simple Models:
  • Crossover Cable
  • Inverter Delay Line
  • Ring Oscillator
  • Timescales and Delays
  • The Classic Testbench:
  • The initial Construct
  • Applying Stimulus Data
  • Generating Clocks
  • Monitoring Response
  • Stimulus/Response:
  • One-Time Pulses
  • Using fork-join
  • Complex Waveforms
  • Random Stimuli
  • Using $monitor
  • Managing Simulation:
  • File Management and I/O
  • Parameters; Defines
  • Avoiding Race Conditions
  • Block-Level Case Study
  • Day 2: Synthesis
  • Literal Bit Vectors
  • The always Construct
  • RTL Gate Logic:
  • Bused NAND4 Gate
  • A 3:8 Decoder
  • Conditionals and Loops
  • RTL Registered Logic:
  • D-Register with Enable
  • Serial-Parallel Converter
  • Four-Bit Up Counter
  • Combination-Lock FSM
  • Advanced Features:
  • Using 2-D Arrays
  • The generate Loop
  • Functions and Tasks
  • Bus-Functional Models
  • In-Class Coding Exercises Included!

WHO SHOULD ATTEND?
  • Engineers who intend to design, verify, test, or support ASICs or FPGAs, but who are not yet proficient in Verilog
  • Those who need to be aware of coding insights and subtle pitfalls
This course includes a course manual filled with color illustrations.

INSTRUCTOR:

Chip Dancak spent ten years at Synopsys, where he developed several of the company's most successful customer-training workshops. Prior to joining Synopsys, he worked at other EDA companies, Lockheed, and Intel. He has presented workshops and seminars in North America, Europe, and Asia. Chip teaches Verilog at U. California Extension (in Silicon Valley). He holds MS degrees in EE and device physics. He is currently developing training for SystemVerilog—the next generation


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