Wafer Level Reliability

As CMOS technology is scaled down, reliability of NMOS and PMOS transistors is affected by hot carrier effects (HCI), gate oxide degradation with time (TDDB) and interconnects degradation due to electro-migration effect (EM). Below 0.18 micron node new reliability issues emerge such as NBTI, PBTI, soft breakdowns and electro-migration type failures in Cu/Low- K interconnect systems.

This course gives detailed understanding of CMOS reliability at the transistor and interconnects level. The course teaches physics behind various degradation mechanisms, methodology of evaluation of these effects and lifetime measurements at Wafer Level. Impact on product reliability is explained. Also formulation of circuit design rules to ensure adequate product lifetime is explained. Emerging reliability failure modes below 0.18 micron node and their methods of evaluation are discussed.

CMOS device and interconnect reliability is directly impacted by process technology, process integration, FAB equipment/materials, FAB defects and circuit design-rules. In this course we link the causes of the reliability to these areas. Set-up of wafer level monitors for quick feed back to FAB and reliability areas is also explained. The course helps building-in reliability (BIR) into process and designs.