Introduction to Integrated Yield Management
Quick Ramp DFM Best Practices
Now offering a one-day Yield Management workshop focusing on
QuickRampDFM™ Best Practices
is a HIGH LEVEL Yield Management - Quick Ramp Overview of faster Product “Time-to-Money” for FAB or
Fabless Companies.
The Workshop benchmarks methodologies against the world’s best by providing an intensive and interactive module series
to achieve the highest level of semiconductor productivity.
How can you benefit by signing up for the Yield Management Quick Ramp™ Workshop? You will learn Product Lifecycles; NPI Pro, Fault Pro, Default Pro, Analysis Pro,
Process Pro, Structure Pro, Speed Pro, Project Pro, Defect Models, Modeling Product Yield, Systematic Faults and have a group exercise.
All participants will find value by attending this workshop.
WHO SHOULD ATTEND?
Engineers, Managers and Support Personnel for: |
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Engineers / Managers / Support Personnel
Device Structure Development
Process Development & Integration
Product Design/Product Engineering
Library & Yield Characterization
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Process Operations
Test & Test Analysis
Physical Failure Analysis
Fab/Foundry Operations Support
Equipment, Materials & Supply Vendors
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WHAT THIS 1 DAY COURSE COVERS: |
Introduction and Objectives Expectations and background
QuickRampDFM™ Best Practices is a HIGH LEVEL QUICK RAMP OVERVIEW of faster Product “Time-to-Money”
for Fab or Fabless Companies. It features:
Product Lifecycles; NPI Pro [feasibility / development / manufacturing]
Fault Pro [limited yield concept / macro & micro models]
Defect Pro [yield scaling]
Analysis Pro [root cause analysis: zones / product sensitivity];
Process Pro [operations / recipes / monitors / particles / pattern defects];
Structure Pro [design / critical structures / entitled yield]
Speed Pro [cycle time / queueing/ wip]
Project Pro [project management / communication / problem solving]
Fault Pro explores Fault Concepts for design / parametrics / random defects; micro models & die windowing for
systematic vs random yield; clustering; defect distributions; fail probability; and the critical area concept to scale yield between designs & to
predict yields before any silicon processing.
Defect Proexplores in depth Defect Models for yield by die size / feature size / circuits / shrinks / new generation.
Advanced analysis & scaling techniques and Modeling Product Yield in a foundry are explored. A Defect Pro exercise
completes this module.
Defect Pro Group Exercise
Analysis Pro explores the many types of
Systematic Faults using analytical techniques for design, parameter & test limited yield,
including techniques of design schmoos, wafer zones, wafer patterns, process windows, time slides,
product / parameter sensitivities [correlations / distributions], and equipment commonality.
Calculations of design / parametric / test limited yield are included.
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Included in this course is a manual filled with color illustrations. |
INSTRUCTOR: |
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Bob Carlson worked for the semiconductor division at IBM where he developed many of the yield
management techniques and test structures for yield enhancement. In the late 70’s, Bob’s engineering team achieved world-class photo limited yields to maximize the 3000 WSD fab output. In the early 80’s, his team brought on line the world’s first 5-inch CMOS fab and piloted the first yielded 8-inch wafers. Bob was the manager of IBM’s high performance bipolar semiconductor development and pre-production fab where his team developed the fastest, densest bipolar memory and logic products for IBM mainframes. Bob was part of the IBM Global Services organization providing Lean Manufacturing Implementation and Concepts Consulting (Cycle-Time) to clients. In 1994 he left IBM to provide industry Cycle Time and Yield Management consulting. Bob holds BS and MS Degrees in Electrical Engineering from the University of Maine.
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"We Exceed Your Expectations!"
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