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PT  International, LLC  Semiconductor Training

3D Stacking and TSV

 

After more than a decade the industry continues to recognize the power of the third dimension in package and sub-system assembly for the implementation of highly integrated electronic products. 3D assembly and packaging of both active and passive devices opens a new world of performance and integration to system designers. Numerous approaches reported and demonstrated include those based on package stacking (package-on-package, origami, and edge stacked modules) and those based on die stacking (wire bond, mixed technology, edge redistribution, and through-silicon-via or TSV).

TSV stands out from the others as a 3D device integration approach as opposed to 3D packaging method. Consequently, through silicon via technology presents unique opportunities and challenges. For example, TSVs promise unrivaled performance improvements due to short, low impedance interconnect and high silicon efficiency. On the other hand, no other 3D approach disrupts the existing supply chain so dramatically.

 This course covers both the fundamental and advanced technologies that today produce stacked chip packages and assemblies as well as stackable packages for implementation of highly integrated electronic products. These include the challenges of die thinning, thin die attach, multi-level wire bonding, mixed technology die attachment and bonding, flip chip, TAB and TSV technologies. Substrate selection for various 3D packaging techniques including silicon tiles, flex circuit origami and specialty interposers concludes the chip stacking section of the course. Several examples of specific 3D package structures demonstrate both the power and limitations of these approaches.

Further considerations for 3D electronics include stackable packages based on flex and rigid substrate approaches, integrated system-in-package techniques and multilayer, embedded passive technologies. Additional coverage of SMT design and assembly implications rounds out the technical content of the course. Using multiple examples of 3D packages in actual usage today, the course also presents a review of the drivers, economics, and intellectual property landscape behind 3D packaging.

This full day course provides a broad perspective of current and emerging 3D assembly, packaging and integration alternatives and includes assessments of technical and market opportunities and challenges.
 

What the Course Covers:

  • 3D Package Trends
  • Consumer Driven Food Chain Reliability at Low Cost
  • Market Growth Alternatives
  • Drivers for 3D Packaging
  • Portable Products RD & Microwave Complexity
  • Performance Reliability
  • Form Factor & Weight
  • Modular Upgradeability
  • 3D Package Applications
  • Military & Aerospace
  • Memory
  • Implantable Medical Devices
  • Mobile Telephony
  • Detector Arrays
  • Netbooks/Tablets
  • Die Stacking
  • Wire Bond
  • Mixed Technology
  • Edge Redistribution
  • Through Silicon Via
  • Stacked Packages
  • Package on Package
  • Origami Edge Stacked Modules
  • Stacked Modules
  • Vertical Stacks
  • Horizontal Stacks
  • Sensor Stacks
  • Enabling Technologies
  • Die/Wafer Thinning
  • Thin Die/Wafer Handling
  • Wire Bond to Thin Die
  • TSV Formation & Filling
  • Wafer Alignment & Bonding
  • Open 3D Issues
  • Test & Design
  • Thermal Management
  • Cost-of-Ownership
  • Supply Chain Disruption
  • Infrastructure Development
  • 3D Assembly Implications
  • Small High I/O Packages
  • CTE Mismatches
  • Thinner/Thicker Packages
  • Packages as Sub-Assemblies
  • Combinations of Diverse Technologies
  • Economics of 3D Packaging
  • Margin Stacking
  • Design Amortization
  • Landscape for 3D Packaging 

Who Should Attend:

Any one wanting  an understanding of the basics of 3D stacking and TSV

Next Schedule Date and Location:

Only offer at client's site

Price:$8,900 USD for up to 14 students