This 1 day course explains the concepts of CMOS digital logic at an easy-to-grasp, intuitive level. It’s ideal for all corporate professionals who interact with, manage, or support ASIC and FPGA designers. Starting with simple pushbutton models, the course covers how nMOS and pMOS transistors work, then progresses to the operation of logic gates and flip-flops. A simple yet practical example, RGBMUX, is threaded through the material to illustrate logic
synthesis using Verilog or VHDL. Speed optimization, logic simulation, and static timing analysis concepts are also covered. The course looks ahead to emerging design and layout trends, such as physical synthesis and signal integrity. Some highlighted topics are: *How hardware engineers use RTL languages (Verilog/VHDL) to describe and synthesize logic. *Why every logic function needs to be simulated before a chip is taped out. The course includes a detailed flowchart of the ASIC design process, showing how EDA tools such as logic synthesis, static timing analysis, place-and-route, DRC/ERC checking, and GDS2 files fit into the front- and back-end flow.
What the Course Covers:
This course will provide the student with a conceptual understanding of how a digital IC is designed and verified. The student will see how logic gates make simple decisions, and will find out why there's a critical limit to the clocking speed of every chip. The student will also understand how front- and back-end design activities like logic synthesis and place-and-route fit into the overall concept to silicon IC flow. The student will be able to communicate and negotiate with designers, and better evaluate their needs for computing resources, EDA software, etc.
Who Should Attend:
Anyone wanting an understanding of CMOS Logic Design
Next Schedule Date and Location:
Only offer at clients' site
$8,900 USD for 14 students)
Contact us if interested in an on site training program