This 2-day course is designed to guide the student to an entry-level understanding of the actual processes used in generating a topological layout for a CMOS integrated circuit. The seminar will also walk the attendee through the major steps involved in determining what is to be built as defined by marketing, circuit implementation, and design engineering. The student will learn actual floor planning and transistor layout techniques. This is followed by descriptions of the processes that follow the layout through the finished product including the effect of die size on yield.
What the Course Covers:
After completing the two-day seminar, the student will be able to understand the major elements of an IC development flow. This includes being able to draw circuits of simple complexity using CMOS transistors and applying good industry layout practices to determine whether the layout is correct to the schematic.
Who Should Attend:
Anyone wanting an understanding CMOS Digital and Analog layout design
Next Schedule Date and Location:
Only offer at clients' site
$12,900 USD for 14 students
Contact us if interested in an on site training program