SEMICONDUCTOR MEMORIES 101

This  2 day course seeks to provide practical design knowledge for designing memory arrays. The primary goal of this course is to allow the VLSI chip designers and others interested in memory technologies to understand memory design techniques and issues, enabling them to design a memory array from start to finish. 

What the Course Covers:

  • Intro to Semiconductor Memories
  • SRAM cell structure and design
  • Cell Structure
  • Basic Operations
  • Sample Output
  • Cell Stability
  • Noise Margin
  • Design Considerations
  • Alternative SRAM based designs
  • Array Architecture
  • Basic memory access concept
  • Basic array structure
  • Wordline and bitline design
  • Decoders, muxes, and I/O circuitry
  • Array bisection
  • Hierarchial design and banking
  • Address mapping to physical location
  • Peripheral circuitry Row decoder and driver
  • Sensing circuits
  • Write drivers
  • Prechargers
  • Column decoders and muxes
  • Timing diagram and operations
  • Modeling and simulation introduction
  • Common control signals overview
  • Basic operation timing diagrams
  • Critical timing relationships
  • Performance parameters and test methods
  • Key AC/DC performance parameters
  • Examples of different memory faults
  • Functional test Scam based test
  • Parellel pin test
  • Built in self test
  • Refresh Application interface and controller
  • Data word width Ports
  • Pipeline and read / write
  • interleaving Refresh Error and defect management
  • Types of redundancy
  • Soft error introduction
  • Soft error mitigation
  • Additional defect and error mitigation methods
  • Power and power management
  • Components of leakage
  • Leakage power reduction techniques
  • Banking Data encoding
  • Clock power reduction
  • Future trends and other memory technologies
  • Future trends of SRAM TCAM
  • introduction DRAM/eDRAM
  • introduction Flash
  • introduction Discrete vs. embedded differences and applications
  • Other future memory technologies

Who Should Attend:

  • Experienced and starting engineers new to the area of memories
  • Industry managers and professionals desiring background in memories
  • Managing an memory design project
  • Evaluating memory macros from vendors
  • Students and professionals wanting to learn about memory design techniques and issues
  • Anybody interested in learning about memory technologies

Next Schedule Date and Location:

Only offer at client's site

Price: $14,900 USD for up to 14 students

 

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PT  International, LLC  Semiconductor Training