This course, about the device yield-related aspects of the Silicon Wafer is designed to give engineers working in yield improvement, as well as all process engineers and others who are involved in specifying Silicon in IC and MEMS devices, a working knowledge of the defects associated with the Silicon that arise from the vendor as well as those generated through device processing.

Practical Knowledge that will be gained:

Throughout the course, practical knowledge of specific silicon defect and yield-related manufacturing examples will be introduced through a series of Short, one page "Applications Notes" covering topics of interest. Some examples include:

Why does a sacrificial oxide reduce defect densities?
Why thermal heat treatments near 750 C may result in a higher silicon defect density?
A defect and gettering comparison of N/N+ or P/P+ epi in process design
Vendor "remelt" usage and the "Phantom P layer" in EPI.
What is the "shelf life" of stored silicon wafers

A method to distinguish between bulk and surface stacking faultsMethods to Add gettering to SOI wafers How to reduce high temperature leakage currents through the use of EPI In MEMS processing, improved dimension control through the use of SOI
WafersWhat the Course Covers

A Review of the Fundamental Properties of Silicon Silicon Applications Engineering

CZ manufacturing techniques Epitaxial Silicon Manufacturing Techniques SOI Manufacturing Techniques

Grown-in and Process-Induced Defects in CZ

Defects Associated with Epitaxial Silicon

Defects associated with SOI materials

Extrinsic Gettering Intrinsic Gettering by Oxygen

Future Gettering Techniques

Diodes and Defect Interactions, Bipolar Transistors and Defect Interactions, MOS, Transistors and Defect Interactions

: A Review of the Device advantages of Epitaxial, Silicon, Epitaxial, Silicon Selection for Process Optimization

, Oxide,

Quality and Epitaxial silicon

Latch-Up and Epitaxial Silicon

Implant Replacement of Epi.

The Device Advantages of Silicon-On-Insulator Silicon-On-Insulator Materials Choices

Future Applications of Silicon-On Insulator

Silicon Wafer Characterization Techniques

Process/Device/Materials Analysis and Design

Wafer cooling effects

Silicon Specifications for Optimum device Performance

Silicon Wafer Requirements for MEMS Devices

Silicon Wafer requirements for Bulk Micro-Machining Silicon Wafer Requirements for Surface Micromachining

Cavity Wafers

Trough-Silicon Tracks

Who Should Attend:

All personnel who want to gain a fundamental understanding of how the Silicon wafer impacts device process yields, including:

 Yield Improvement Engineers

 Process Engineers

 Quality Engineers involved with Silicon

 Supply Chain Management

Next Schedule Date and Location:

Only offer at clients site

Price: $8,900 USD for up to 14 students

Silicon Substrate Preparation
 Identifying and preventing defects of the substrate for ICs and MEMS devices



PT International, LLCSemiconductor Training