PT  International, LLC  Semiconductor Training

Wafer level reliability

This is a 2 day course. As CMOS technology is scaled down, reliability of NMOS and PMOS transistors is affected by hot carrier effects (HCI), gate oxide degradation with time (TDDB), and interconnect degradation due to electro-migration effect (EM). Below 0.18 micron node new reliability issues emerge such as NBTI, PBTI, soft breakdowns and electro-migration type failures in Cu/Low- K  interconnect systems.    This course teaches the physics behind various degradation mechanisms, methodology of evaluation of these effects and measurements of lifetimes. Impact on product reliability is explained. Also formulation of design rules to ensure adequate product lifetime is explained. Emerging reliability failure modes below 32 nn node and their methods of evaluation are discussed. 


Who Should Attend:

Process  Engineers

Product Engineers

Device Engineers

Design Engineers


Next Schedule Date and Location:

Only offer at clients' site


$12,900 for 14 students

Contact us if interested in an on site training program