Introduction to Verilog Design

Professional semiconductor training with 46+ years of industry expertise

Course Overview

Hardware description languages (HDLs) use statements to define, simulate, synthesize and physical layout. Verilog is used as a HDL, can be used to design PALs, ASICs and FPGAs. This course teaches the student how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of the Verilog language is explained.

What the Course Covers

Introduction to SystemVerilog

  • Benefits of HDLs over other design entry methods
  • Modeling different levels of abstraction
  • Reusability and documentability
  • SystemVerilog language overview
  • Design flow and methodology

Data Types and Language Syntax

  • Basic Verilog data types
  • SystemVerilog data types
  • Variable declarations and assignments
  • Verilog language syntax and structure
  • Coding style and best practices

Advanced Data Structures

  • Structures, Unions, and Arrays
  • Packed and unpacked arrays
  • Dynamic arrays and queues
  • Associative arrays
  • Data manipulation techniques

Operators and Control Flow

  • Additional Operators in SystemVerilog
  • Procedural Statements and Flow Control
  • Conditional statements and loops
  • Case statements and pattern matching
  • Blocking vs non-blocking assignments

Functions, Tasks, and Modular Design

  • Functions, Tasks, and Packages
  • Module instantiation and hierarchy
  • Parameter passing and configuration
  • Code reusability techniques
  • Design organization and structure

Interfaces and Package Types

  • Interface design and implementation
  • Package types and organization
  • Inter-module communication
  • Design verification concepts
  • Simulation and synthesis considerations

Applications

This course prepares students to design:

  • PALs (Programmable Array Logic)
  • ASICs (Application-Specific Integrated Circuits)
  • FPGAs (Field-Programmable Gate Arrays)
  • Digital systems and hardware accelerators

Who Should Attend

Anyone wanting an understanding of Verilog design, including digital designers, verification engineers, FPGA developers, and hardware engineers.

Ready to Register?

$12,900 USD

For up to 14 students (2 Days)

Register Now
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Duration
2 Days
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Format
On-site Training

Need More Information?

Phone: 636-343-1333

Email: heather@pti-inc.com