Course Overview
This 2-day course seeks to provide practical design knowledge for designing memory arrays. The primary goal of this course is to allow the VLSI chip designers and others interested in memory technologies to understand memory design techniques and issues, enabling them to design a memory array from start to finish.
What the Course Covers
Introduction to Semiconductor Memories
- Overview of memory technologies
- Memory classification and types
- Applications and market trends
- Performance metrics and specifications
SRAM Cell Structure and Design
- SRAM cell structure and design
- Cell structure and basic operations
- Sample output and cell stability
- Noise margin and design considerations
- Alternative SRAM based designs
Array Architecture
- Basic memory access concept
- Basic array structure
- Wordline and bitline design
- Decoders, muxes, and I/O circuitry
- Array bisection
- Hierarchical design and banking
- Address mapping to physical location
Peripheral Circuitry
- Row decoder and driver
- Sensing circuits
- Write drivers
- Prechargers
- Column decoders and muxes
Timing and Operations
- Timing diagram and operations
- Modeling and simulation introduction
- Common control signals overview
- Basic operation timing diagrams
- Critical timing relationships
Performance and Testing
- Performance parameters and test methods
- Key AC/DC performance parameters
- Examples of different memory faults
- Functional test and scan-based test
- Parallel pin test
- Built-in self test (BIST)
Advanced Topics
- Refresh application interface and controller
- Data word width and ports
- Pipeline and read/write interleaving
- Types of redundancy
- Soft error introduction and mitigation
- Additional defect and error mitigation methods
Power Management
- Components of leakage
- Leakage power reduction techniques
- Banking and data encoding
- Clock power reduction
Future Trends and Technologies
- Future trends of SRAM
- TCAM introduction
- DRAM/eDRAM introduction
- Flash introduction
- Discrete vs. embedded differences and applications
- Other future memory technologies
Who Should Attend
- Experienced and starting engineers new to the area of memories
- Industry managers and professionals desiring background in memories
- Those managing a memory design project
- Engineers evaluating memory macros from vendors
- Students and professionals wanting to learn about memory design techniques and issues
- Anybody interested in learning about memory technologies