Semiconductor Manufacturing for the AI Era

The Physical Execution of the AI Supercycle.

A fab-grade reference designed for industry veterans and advanced students navigating the Angstrom era.

The Bottleneck Isn't Software. It's Manufacturing.

The next decade of artificial intelligence compute will not be gated by algorithms; it is strictly gated by the physical limits of materials science, reticle sizes, and thermal dissipation.

Semiconductor Manufacturing for the AI Era is not a high-level industry summary. Co-authored by Denny Frye and Cory Vincent Frye for PT International LLC, this text decodes the entire advanced semiconductor lifecycle, providing unparalleled technical depth across logic, memory, and heterogenous packaging.

"Whether you are structuring a university curriculum, training foundry engineers, or aligning your equipment supply chain with the demands of the Angstrom era, this text provides the foundational architecture."
// YIELD_ENTITLEMENT_MODEL.py
def calculate_yield(defect_density, area):
"""Poisson Yield Model for reticle-limit AI chips"""
return math.exp(-area * defect_density)
// ADVANCED_PACKAGING.config
ARCHITECTURE: CoWoS
INTERCONNECT: Cu-Cu_Hybrid_Bonding
MEMORY_STACK: HBM3_12Hi
LITHOGRAPHY: 0.55_High-NA_EUV

Key Technical Pillars Decoded

Master the atomic-scale engineering required to fabricate the hardware powering Generative AI.

Nano-Fabrication

Granular analysis of the atomic-scale additive and subtractive processes required for sub-3nm nodes, including ALD, ALE, and Plasma Doping (PLAD).

Transistor Evolution

The geometric and thermodynamic transition from planar limits to FinFET, Gate-All-Around (GAA/RibbonFET), and the Complementary FET (CFET) architectures.

Advanced Packaging

The complete engineering reality of escaping the reticle limit. Master the mechanics of CoWoS, Cu-Cu Hybrid Bonding, and 3D stacking of HBM systems.

Next-Gen Lithography

The optical physics, RLS tradeoffs, and deployment realities of 0.55 High-NA EUV systems, Metal Oxide Resists (MOR), and anamorphic magnification.

Inside the Book

Rich, highly-accurate infographics visually dissect complex physics and mechanical fab architectures.

Chapter 1 Preview Chapter 3 Preview Chapter 6 Preview Chapter 11 Preview Chapter 18 Preview Chapter 20 Preview Chapter 24 Preview

Complete Curriculum

Structured to build knowledge sequentially from fundamental physics to final cleanroom operations across 29 comprehensive chapters.

    PART I & II: Foundation & Infrastructure
  • Ch 1: The Semiconductor Industry in the AI Era
  • Ch 2: Semiconductor Device Physics for Nanoscale Nodes
  • Ch 3: Advanced Transistor Architectures
  • Ch 4: Fab Architecture and Cleanroom Design
  • Ch 5: Contamination Control and Cleaning Technology
  • Ch 6: Gases, Liquid Chemicals, and Ultra-Pure Water
  • Ch 7: Vacuum Technology for ULSI Applications
  • PART III & IV: Wafer & FEOL Processing
  • Ch 8: Silicon Single-Crystal Growth
  • Ch 9: Wafer Manufacturing & Specialty Substrates
  • Ch 10: Thermal Processing and Diffusion
  • Ch 11: Ion Implantation and Doping
  • Ch 12: Oxidation and High-k Dielectrics
  • Ch 13: Plasmas Used in Microchip Manufacturing
  • Ch 14: Thin-Film Fundamentals and CVD/ALD
  • Ch 15: Epitaxy and Advanced Silicon Structures
  • PART V & VI: Lithography, Etch & BEOL
  • Ch 16: Lithography I: Photoresist Materials
  • Ch 17: Lithography II: Image Formation & Optics
  • Ch 18: Lithography III: EUV & High-NA Mask Tech
  • Ch 19: Wet Etching and Dry Atomic-Scale Etching (ALE)
  • Ch 20: Chemical Mechanical Polishing (CMP)
  • Ch 21: PVD and Angstrom-Era Metallization
  • Ch 22: Interconnect Technology and Air Gaps
  • PART VII & VIII: Packaging, Test & Operations
  • Ch 23: Semiconductor Memory (HBM & 3D NAND)
  • Ch 24: Advanced Packaging (Hybrid Bonding & Chiplets)
  • Ch 25: Materials Characterization and Electrical Test
  • Ch 26: TCAD and Process Simulation
  • Ch 27: Wafer Fab Operations and Yield Management
  • Ch 28: Environmental, Health, Safety & Sustainability
  • Ch 29: Fab Maintenance & Troubleshooting Case Studies

The Authors

With decades of combined experience spanning process engineering, supply chain logistics, and the geopolitical history of silicon, Denny Frye and Cory Vincent Frye have codified the hardware innovations that make the AI supercycle possible.

Their mission is to provide the definitive training architecture for the next generation of semiconductor engineers, equipping them with the hard scientific realities required to push Moore's Law into the Angstrom era.

Endorsed by Industry Leaders

"Denny presented a wonderful semiconductor seminar! He should create a textbook with his knowledge and expertise!"

- Dr. Jeffery Buck

Dean & VP of School of Business, Purdue University

"He does an excellent job of making complex ideas easy to understand."

- Andy Ahrendt

VP of National Manufacturing, Clean Rooms

"He has an in-depth firsthand as well as academic knowledge of the subject, most of all his teaching/training style is most engaging and very easy to follow regardless of your own background knowledge."

- Azmat Siddiqi

Quality Director, Applied Materials

Semiconductor Textbook Cover

Architecting the physical infrastructure of the AI Era.

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Phone: 636-343-1333

Email: heather@pti-inc.com