Definition
Hold time is the minimum interval after the relevant active clock edge during which input or data must remain stable so a sequential circuit or clocked interface can capture it correctly.
Application
Static timing analysis and interface timing closure check hold time together with setup time to prevent incorrect data capture in IC, FPGA, and memory interfaces.
Related search terms
data hold time
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Related concepts
Evidence and further reading
- Evidence from intel.comhttps://www.intel.com/programmable/technical-pdfs/683741.pdf
- Evidence from edc.intel.comhttps://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/eagle-stream/platform-electrical-data-sheet/serial-vid-svid-interface-ac-timing-specifications/