Static Timing Analysis

Definition

A timing-verification method that calculates signal delays along circuit paths and checks them against timing constraints without simulating the circuit’s logical operation for sets of input test vectors.

Application

Used to identify setup, hold, and other timing violations from a circuit netlist, cell timing models, interconnect delays, and timing constraints during digital IC implementation.

Related concepts

• Standard Cell
• Netlist
• Logic Synthesis

Evidence and further reading

• Evidence from synopsys.comhttps://www.synopsys.com/glossary/what-is-static-timing-analysis.html
• Evidence from github.comhttps://github.com/parallaxsw/OpenSTA