Definition
Automated transformation and optimization of RTL or another logic representation into an implementation-oriented gate-level netlist under design constraints.
Application
Used in digital IC design to map functional RTL into cells/netlists for downstream timing, physical-design, and verification flows.
Related search terms
RTL synthesis; digital synthesis
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Related concepts
Evidence and further reading
- Evidence from synopsys.comhttps://www.synopsys.com/glossary/what-is-synthesis.html
- Evidence from cadence.comhttps://www.cadence.com/en_US/home/resources/datasheets/virtuoso-digital-implementation-ds.html