PTI technical training
Introduction to CMOS Layout Design
Build knowledge of CMOS layout design and integrated circuit layout practices. Explore PTI's introductory curriculum and available training options.
Course Overview
This 2-day course is designed to guide the student to an entry-level understanding of the actual processes used in generating a topological layout for a CMOS integrated circuit. The seminar will also walk the attendee through the major steps involved in determining what is to be built as defined by marketing, circuit implementation, and design engineering. The student will learn actual floor planning and transistor layout techniques. This is followed by descriptions of the processes that follow the layout through the finished product including the effect of die size on yield.
What the Course Covers
IC Development Flow
- Major elements of an IC development flow
- Steps from marketing requirements to finished product
- Circuit implementation and design engineering
- Design flow methodology
CMOS Circuit Design
- Drawing circuits of simple complexity using CMOS transistors
- CMOS digital circuit fundamentals
- CMOS analog circuit basics
- Circuit schematic to layout correlation
Layout Design Fundamentals
- Topological layout processes for CMOS integrated circuits
- Floor planning techniques
- Transistor layout techniques
- Layout design rules and constraints
Industry Layout Practices
- Good industry layout practices
- Layout verification techniques
- Determining whether layout is correct to the schematic
- Design rule checking (DRC)
- Layout vs. schematic (LVS) verification
Post-Layout Processes
- Processes that follow the layout through the finished product
- Effect of die size on yield
- Manufacturing considerations
- Yield optimization strategies
Learning Outcomes
After completing the two-day seminar, the student will be able to understand the major elements of an IC development flow. This includes being able to draw circuits of simple complexity using CMOS transistors and applying good industry layout practices to determine whether the layout is correct to the schematic.
Who Should Attend
Anyone wanting an understanding CMOS Digital and Analog layout design.