Clock Skew

Definition

The difference in arrival time of the same clock edge at different sequential elements in a synchronous digital circuit.

Application

Used as a key timing-closure metric in physical design because excessive skew can reduce setup or hold margin and cause incorrect data capture; clock-distribution design attempts to control both skew and latency.

Related concepts

• Static Timing Analysis
• Setup Time
• Hold Time
• Signal Integrity

Evidence and further reading

• Evidence from community.cadence.comhttps://community.cadence.com/cadence_blogs_8/b/di/posts/clock-tree-synthesis-cts-the-backbone-of-physical-design
• Evidence from resources.pcb.cadence.comhttps://resources.pcb.cadence.com/blog/2019-how-to-prevent-clock-skew-in-pcb-design