Definition
Layout Versus Schematic (LVS) is physical-verification checking that the devices and connectivity extracted from an IC layout match the intended schematic or source netlist.
Application
Used before tapeout to detect missing, extra, shorted, misconnected, or parameter-mismatched devices and nets between physical implementation and circuit intent.
Related search terms
LVS verification; layout-to-schematic comparison
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Related concepts
Evidence and further reading
- Evidence from support1.cadence.comhttps://support1.cadence.com/public/docs/content/20479466.html
- Evidence from static.sw.cdn.siemens.comhttps://static.sw.cdn.siemens.com/siemens-disw-assets/public/81836/en-US/Siemens-SW-Improving-productivity-with-more-efficient-LVS-debug-WP-81836-C2.pdf