Definition
Parasitic extraction is the calculation of unintended electrical resistance, capacitance, inductance, and related interconnect parameters from physical layout geometry.
Application
Used after layout to build parasitic models for timing, signal-integrity, power-integrity, and circuit-performance analysis before signoff.
Related concepts
Evidence and further reading
- Evidence from ansys.synopsys.comhttps://ansys.synopsys.com/products/electronics/ansys-q3d-extractor
- Evidence from siemens.comhttps://www.siemens.com/en-gb/products/ic/calibre-design/circuit-verification/xact/