Definition
A short-channel MOSFET effect in which a higher drain voltage lowers the source-to-channel potential barrier, reducing threshold voltage and increasing off-state carrier injection.
Application
Used as a key electrostatic-control metric for scaled transistors; device architecture, channel and junction engineering are optimized to reduce DIBL and associated off-state leakage.
Related search terms
Drain-induced barrier lowering; drain-induced threshold lowering
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Related concepts
Evidence and further reading
- Evidence from bpb-us-w2.wpmucdn.comhttps://bpb-us-w2.wpmucdn.com/sites.coecis.cornell.edu/dist/4/81/files/2017/03/ece3150_handout26-2niap9q.pdf
- Evidence from research.ibm.comhttps://research.ibm.com/publications/vlsi-limitations-from-drain-induced-barrier-lowering