Definition
An IC physical-verification check that tests a design against process-defined electrical connectivity, path and device rules that are not captured by purely geometric design-rule checking.
Application
Used before tapeout to identify electrical-layout problems such as invalid connectivity, floating or nonfunctional devices and power/ground path issues, complementing DRC and layout-versus-schematic verification.
Related search terms
Electrical rules checking; electrical-rule verification
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Related concepts
Evidence and further reading
- Evidence from cadence.comhttps://www.cadence.com/en_US/home/resources/datasheets/assura-physical-verification-ds.html
- Evidence from support1.cadence.comhttps://support1.cadence.com/public/docs/content/20419245.html