Definition
The portion of semiconductor wafer fabrication in which isolation, wells, gates, channels, source/drain regions, and other active device structures are formed before the main interconnect stack.
Application
Used to fabricate and scale transistor/device structures whose contacts are subsequently connected during MOL/BEOL processing.
Related search terms
Front End of Line; FEOL
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Related concepts
Evidence and further reading
- Evidence from intel.comhttps://www.intel.com/content/www/us/en/history/museum-terminology.html
- Evidence from semiengineering.comhttps://semiengineering.com/knowledge_centers/integrated-circuit/