Definition
A logic-integration approach that moves power-routing structures from the wafer frontside to the backside so power delivery is separated from much of the frontside signal-interconnect network.
Application
Used as an advanced-node scaling technique to reduce frontside BEOL routing congestion, lower power-delivery resistance and IR drop, and create additional routing freedom for dense standard cells.
Related search terms
Backside power; backside power distribution
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Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/how-power-chips-backside
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/backside-power-delivery-options-dtco-study