Definition
A transistor aging mechanism in which sustained gate bias at elevated temperature causes charge trapping and defect-related changes that shift threshold voltage and degrade device electrical performance over time.
Application
Used in semiconductor reliability qualification and lifetime modeling; NBTI is especially important for pMOS devices and PBTI for nMOS or high-k gate stacks.
Related search terms
Bias-temperature instability
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Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/novel-approach-improving-gate-stack-reliability
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/dc-reliability-high-k-gan-si-mos-hemts-mm-wave-power-amplifiers