Definition
An advanced transistor-integration contact formed from the wafer backside to connect directly to a transistor source/drain region or its local contact structure, rather than routing that connection only through the conventional frontside interconnect stack.
Application
Used in emerging backside-power and CFET integration to shorten power/contact paths, reduce frontside routing congestion and support cell scaling; implementation requires wafer bonding, extreme backside thinning, precise backside alignment, isolation and contact etch.
Related search terms
Backside source/drain contact; direct backside power contact
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Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/press/imec-proposes-double-row-cfet-a7-technology-node
- Evidence from newsroom.intel.comhttps://newsroom.intel.com/intel-foundry/intel-foundry-gathers-customers-partners-outlines-priorities