Definition
A field-effect transistor architecture in which the gate wraps around the semiconductor channel to provide strong electrostatic control.
Application
Used for continued CMOS scaling beyond FinFETs, including stacked nanowire or nanosheet devices with improved short-channel control.
Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/imec-demonstrates-gate-all-around-mosfets-with-lateral-silicon-nanowires-at-scaled-dimensions
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/imec-demonstrates-world-s-first-vertically-stacked-gate-all-around-si-nanowire-cmos-transistors