Definition
The center-to-center spacing of neighboring gate structures, often specified as contacted gate pitch in advanced logic scaling.
Application
Used as a density/scaling metric that constrains transistor placement and standard-cell area in advanced CMOS.
Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/imec-presents-forksheet-device-as-the-ultimate-solution-to-push-scaling-towards-the-2nm-technology-node
- Evidence from imec-int.comhttps://www.imec-int.com/en/press/imec-demonstrates-functional-monolithic-cfet-devices-stacked-bottom-and-top-contacts