Definition
A dielectric sidewall structure formed beside a transistor gate that electrically separates the gate from source/drain regions and helps define self-aligned device geometry.
Application
Used to control source/drain recess or implant alignment, gate-to-contact isolation, and parasitic capacitance in scaled transistors.
Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/press/imec-demonstrates-functional-monolithic-cfet-devices-stacked-bottom-and-top-contacts
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/imec-demonstrates-optimized-process-flows-for-high-performance-ge-based-devices