Definition
A serial chain of scan cells that acts as a shift register in scan mode, allowing internal logic states to be loaded and read out.
Application
Used in design for test to load test patterns, capture circuit responses, and shift those responses out for logic testing.
Related concepts
Evidence and further reading
- Evidence from cs.colostate.eduhttps://www.cs.colostate.edu/~malaiya/pub/Sanyal_final.pdf
- Evidence from synopsys.comhttps://www.synopsys.com/content/dam/synopsys/implementation&signoff/white-papers/SynthesisBased-Test-wp.pdf