Definition
A CMOS device architecture that vertically stacks n-type and p-type field-effect transistors so their separation is moved from the lateral plane into the vertical direction.
Application
Developed for logic scaling beyond nanosheet GAA devices because vertical nFET/pFET stacking can reduce standard-cell footprint and create more routing flexibility at extremely tight pitches.
Related search terms
Complementary FET; complementary field-effect transistor
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Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap
- Evidence from imec-int.comhttps://www.imec-int.com/en/press/imec-demonstrates-functional-monolithic-cfet-devices-stacked-bottom-and-top-contacts