Definition
An integration approach in which active semiconductor dies, wafers or device layers are vertically stacked and electrically interconnected to increase functional density and shorten interconnect paths.
Application
Used in vertically stacked logic and memory, HBM-class structures, wafer-to-wafer or die-to-wafer bonding, and other packages where footprint and interconnect length must be reduced.
Related search terms
3D IC; 3D stacking
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Related concepts
Evidence and further reading
- Evidence from ase.aseglobal.comhttps://ase.aseglobal.com/3d-ic-packaging/
- Evidence from semi.orghttps://www.semi.org/en/communities/heterogeneous_integration_roadmap