Definition
A standardized design-for-test architecture that places scan cells at an integrated circuit's I/O boundary and accesses them through a serial Test Access Port to observe or control pins and test interconnections.
Application
Used for board and package interconnect testing, device access, debug and programming when physical probing of dense assemblies is impractical; it is standardized by IEEE 1149.1.
Related search terms
Boundary-scan test; JTAG boundary scan
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Related concepts
Evidence and further reading
- Evidence from standards.ieee.orghttps://standards.ieee.org/ieee/1149.1/10977/
- Evidence from sagroups.ieee.orghttps://sagroups.ieee.org/1149-1/