Definition
Signal-propagation delay associated with charging and discharging interconnect capacitance through interconnect resistance; it increases with the parasitic resistance and capacitance of the wiring.
Application
Used in BEOL timing analysis and interconnect design, motivating lower-resistance conductors and lower-k dielectric materials to reduce wiring delay in advanced integrated circuits.
Related search terms
Resistance-capacitance delay; Interconnect RC delay
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Related concepts
Evidence and further reading
- Evidence from cambridge.orghttps://www.cambridge.org/core/journals/mrs-bulletin/article/abs/integration-of-lowk-dielectric-materials-into-sub025m-interconnects/9EB998AD314A3E46A176708B9F7008C3
- Evidence from ansys.comhttps://www.ansys.com/it-it/resource-center/webinar/roughness-effect-on-next-gen-cu-interconnects