Definition
The electrical resistance of a via connection between interconnect levels, including contributions from the conductor and interfaces in that connection.
Application
Used to evaluate interconnect delay and compare via geometries or materials when optimizing chip wiring.
Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/imec-magazine/imec-magazine-november-2018/the-supervia-a-promising-scaling-booster-for-the-sub-3nm-technology-node
- Evidence from research.ibm.comhttps://research.ibm.com/publications/impact-of-line-and-via-resistance-on-device-performance-at-the-5nm-gate-all-around-node-and-beyond