Definition
In chip interconnects, a vertical conductive connection between wiring layers.
Application
Connects wiring levels so signals and power can pass through a chip's interconnect stack.
Related concepts
Evidence and further reading
- Evidence from imec-int.comhttps://www.imec-int.com/en/imec-magazine/imec-magazine-november-2018/the-supervia-a-promising-scaling-booster-for-the-sub-3nm-technology-node
- Evidence from ir.appliedmaterials.comhttps://ir.appliedmaterials.com/static-files/41a278ec-a155-4703-be30-f56b59cf85f3