PT International LLC · 8-Hour Professional Training Course
Advanced Semiconductor Packaging
Understand the technologies and manufacturing decisions behind chiplets, HBM and high-performance multi-die systems.
Course description
Advanced Semiconductor Packaging is an intensive, instructor-led course covering the architectures, materials, processes and manufacturing controls used to integrate multiple semiconductor dies into high-performance electronic systems.
The course connects chiplets and high-bandwidth memory (HBM) with the technologies that make their integration possible: flip-chip assembly, micro-bumps, through-silicon vias (TSVs), silicon and glass interposers, redistribution layers, thermocompression bonding and hybrid bonding. Participants follow representative process flows and examine how interconnect density, power delivery, heat removal, test coverage and mechanical reliability shape packaging decisions for artificial intelligence (AI) and high-performance computing (HPC).
Emphasis is on understanding how the technologies fit together, where manufacturing problems arise and how to compare their advantages and limitations.
Course outline
Eight modules provide 480 minutes of instruction, including guided application work and discussion.
01 · Packaging architectures and system requirements
45 minutes
- How packaging has evolved from protecting individual dies to enabling system-level integration.
- Compare 2D, 2.5D and 3D architectures; identify the roles of dies, interposers, substrates and package interconnects.
- Packaging requirements for AI accelerators, CPUs, GPUs and high-bandwidth memory (HBM).
- Connect bandwidth, interconnect density, signal integrity, power delivery and thermal limits to architecture choices.
- Place full interposers, local silicon bridges and fan-out redistribution approaches in context.
02 · Chiplets, HBM and multi-die integration
60 minutes
- Compare monolithic designs with functional partitioning across logic, memory, I/O and specialized dies.
- Understand opportunities for process-node selection, IP reuse and reticle-limit extension, alongside packaging and test costs.
- Follow a representative processor-plus-HBM package architecture and its logic-to-memory connections.
- Review die-to-die interfaces and the role of standards such as UCIe; distinguish interface compatibility from complete system interoperability.
- Explain known-good-die screening, residual test risk, assembly yield and the cost of losing multiple dies in one package.
- Discuss electrical, mechanical and thermal co-design across die, package and system boundaries.
03 · Flip-chip assembly, solder bumps and micro-bumps
60 minutes
- Compare flip-chip attachment with wire bonding and identify where each approach is appropriate.
- Follow a representative bumping and assembly flow: under-bump metallization, bump formation, alignment, placement, bonding and underfill.
- Distinguish conventional solder bumps, copper pillars and fine-pitch micro-bump interconnects.
- Compare mass reflow and thermocompression assembly routes; understand how the selected process affects materials and sequence.
- Relate pitch, bump height, coplanarity and alignment to bridging, opens, voids and joint formation.
- Connect underfill properties, intermetallic growth, electromigration and thermal fatigue to interconnect reliability.
04 · Through-silicon vias and 3D process integration
60 minutes
- Explain the different functions of TSVs through silicon and bonding interconnects between adjacent surfaces.
- Compare via-first, via-middle and via-last approaches in relation to device fabrication and integration sequence.
- Walk through deep silicon etching, dielectric isolation, barrier and seed deposition, copper filling and planarization.
- Review temporary wafer support, thinning, backside via reveal and backside interconnect formation.
- Relate TSV geometry to resistance, capacitance, stress and device keep-out considerations.
- Recognize fill voids, liner defects, cracking and handling damage; connect these risks to stacked-memory and logic-integration examples.
05 · Silicon, glass and organic interconnect platforms
60 minutes
- Explain how interposers and redistribution layers route signals and power between dies and the package substrate.
- Review silicon interposers, fine-pitch routing, TSV connections and processor-plus-HBM integration.
- Compare full interposers, local bridges and organic or fan-out redistribution approaches.
- Distinguish a glass interposer from a glass-core package substrate and describe through-glass vias (TGVs).
- Review glass via formation, metallization, adhesion, handling and dimensional-control challenges.
- Compare routing capability, electrical loss, coefficient of thermal expansion, heat removal, yield, supply-chain maturity and cost; separate demonstrated capabilities from development targets.
06 · Thermocompression and hybrid bonding
90 minutes
- Review die-to-die, die-to-wafer and wafer-to-wafer assembly configurations and their alignment and test implications.
- Explain thermocompression bonding through controlled temperature, force, alignment and dwell time.
- Compare solder-based thermocompression with direct copper-to-copper thermocompression; identify their different interface and process requirements.
- Explain hybrid bonding as an interface that combines dielectric-to-dielectric and metal-to-metal connections, commonly copper.
- Follow a representative hybrid-bonding sequence: planarization, surface preparation and activation, alignment, contact and thermal treatment as required by the process.
- Relate cleanliness, copper oxidation and topography, surface roughness, die preparation and overlay to bond quality.
- Compare interconnect pitch, thermal budget, throughput, inspection access and rework limitations across bonding routes.
- Use a process-flow comparison to trace contamination, particles, misalignment, voids and incomplete bonding to likely failure points.
07 · Process integration, test, yield and reliability
75 minutes
- Connect incoming die quality, substrate readiness, bonding, underfill or encapsulation, thermal interfaces and final assembly.
- Place wafer probe, pre-bond screening, intermediate test and final package test within a multi-die manufacturing flow.
- Compare optical inspection, X-ray, acoustic inspection, electrical testing and destructive analysis; understand their coverage and access limits.
- Analyze warpage, coefficient-of-thermal-expansion mismatch, delamination, thermal cycling, moisture-related damage and interconnect degradation.
- Review power density, hot spots, thermal interfaces and heat-removal paths in stacked and side-by-side architectures.
- Discuss process windows, traceability, contamination control, statistical monitoring, throughput and cost per good package.
- Work through a guided defect-and-yield example: distinguish an observed symptom from a confirmed failure mechanism and select useful follow-up checks.
08 · Application exercise, review and discussion
30 minutes
- Compare candidate architectures for a representative AI processor and HBM system using bandwidth, power, thermal, test and manufacturing constraints.
- Map the selected architecture to its principal interconnects, process steps and inspection needs.
- Review the advantages and limitations of each integration approach, then discuss questions and emerging directions.
Total instructional time: 8 hours (480 minutes). Breaks and meal periods are scheduled separately.
Course objectives
After completing this course, attendees will be able to:
- Distinguish 2D, 2.5D and 3D package architectures and explain how packaging affects system performance.
- Explain chiplet partitioning, HBM integration and the practical limits of die-to-die interoperability.
- Describe representative flip-chip and micro-bump process flows and identify their critical controls.
- Outline TSV fabrication and backside processing, including key electrical and mechanical risks.
- Compare silicon interposers, glass interposers, glass-core substrates and organic interconnect approaches.
- Describe thermocompression and hybrid-bonding flows, interface requirements and process tradeoffs.
- Connect contamination, misalignment, voids, warpage and thermal stress to yield and reliability risks.
- Identify where screening, inspection, metrology and electrical testing contribute to a multi-die manufacturing flow.
- Compare packaging options against application requirements without assuming one technology is best for every product.
What attendees will learn
Build a practical framework for following an advanced package from architecture through assembly, test and reliability evaluation.
- Chiplets and HBM: How partitioned logic and memory are combined, and why interfaces, test coverage and package-level economics matter.
- Flip-chip and micro-bumps: How fine-pitch joints are formed and how alignment, materials and assembly conditions affect quality.
- TSVs and backside processing: How vertical connections are fabricated through silicon and integrated with thinning and bonding.
- Silicon and glass interconnect platforms: How interposers, bridges, redistribution layers and substrates serve different routing and integration roles.
- Advanced bonding: How thermocompression and hybrid-bonding processes differ in their interfaces, controls and manufacturing constraints.
- Manufacturing and reliability: How test strategy, inspection coverage, contamination, stress and heat removal influence yield and field performance.
Who should attend
This course is designed for:
- Semiconductor process, equipment and manufacturing engineers.
- Advanced packaging, assembly and integration engineers.
- Research and development engineers.
- Equipment, substrate and materials suppliers.
- Quality, reliability, test and failure-analysis engineers.
- Technical managers and engineering supervisors.
- Semiconductor professionals moving into chiplets, HBM or advanced packaging.
Expected benefits
Participants will gain a structured understanding of the major technologies used in advanced packaging and a shared vocabulary for working across design, wafer fabrication, assembly, equipment, materials, test and reliability teams. They will be better prepared to discuss process requirements, recognize manufacturing risks and ask informed questions when evaluating packaging options for AI, HPC and other demanding applications.
Course format: Instructor-led technical training combining architecture illustrations, process explanations, representative manufacturing examples, guided comparisons and technical discussion.
Course glossary
Prepare for the course or revisit key terms after training.